I am a Research Scientist at Intel Labs. I am broadly interested in high-performance computing (HPC), computer architecture, and compilers with emphasis on program analysis and transformation of irregular applications to make efficient use of heterogeneous parallel architectures, both at the node level and the cluster level.
I received my PhD degree from the Bradley Department of Electrical and Computer Engineering, Virginia Tech. During my PhD research, I worked with Dr. Wu-chun Feng, Changhee Jung, and Yasser Hanafy on novel automation frameworks for performance analysis and runtime adaptation using graph-structured program representations.
Before joining Virginia Tech, I received my MSc. and BSc. degrees in Electronics and Communications Engineering from Cairo University. In the professional world, I worked on the research and development of various computing systems, ranging from wearable devices, to cyber-physical systems, to HPC clusters.